Embodiments of the invention relate generally to semiconductor device packages or electronics packages and, more particularly, to an electronics package that includes an embedded structure containing multiple conductive through-connects and/or resistors. The inclusion of multiple conductive through-connects and/or resistors into a single embedded structure, and the integration thereof along with power devices in the electronics package, provides a simplified manufacturing process, lower cost, and pre-testability of the conductor/resistor structure.
As semiconductor device packages have become increasingly smaller and yield better operating performance, packaging technology has correspondingly evolved from leaded packaging, to laminated-based ball grid array (BGA) packaging, to chip scale packaging (CSP), then flipchip packages, and now buried die/embedded chip build-up packaging. Such embedded chip packages can include one or more packaged components therein in the form of power semiconductor devices, packaged controllers, or other discrete electrical components such as inductors or passive components, to which electrical connections are made by way of metalized interconnects formed in the package structure. The power semiconductor devices in the package may be used as switches or rectifiers in power electronic circuits, such as switched mode power supplies, for example. Most power semiconductor devices are only used in commutation mode (i.e., they are either on or off), and are therefore optimized for this. One such power semiconductor device is a high performance, wideband gap silicon carbide (SiC) MOSFET, which has very fast switching transitions and can be used as a power or high frequency device.
A general construction of an embedded chip package 10 is illustrated in FIG. 1, with a standard technique for manufacturing such an embedded chip package described here below. The manufacturing process typically begins with placement of one or more components—including semiconductor devices 12 and other discrete electrical components 14—onto a dielectric layer 16 by way of an adhesive 18, with the semiconductor devices 12 and associated components 14 being provided in a planar arrangement. Metal interconnects (e.g., copper interconnects) 20 are then electroplated onto the dielectric layer 16 to form a direct metallic connection to the components 12, 14. The metal interconnects 20 may be in the form of a low profile (e.g., less than 200 micrometers thick), planar interconnect structure that provides for formation of an input/output (I/O) system to and from the components 12, 14. A multi-layer ceramic substrate 22 (Alumina with direct bonded copper (DBC), Aluminum Nitride with active metal brazing copper, etc.) is then soldered to a backside of one or more of the components 12, 14 using soldered interconnections for electrical and thermal connectivity, with shims 24 (e.g., copper shims) or other vertical electrical connectors being used as necessary to bring all electrical connections to the multi-layer ceramic substrate 22. The gaps around the components between the dielectric layer and the ceramic substrate are then filled with a dielectric organic material 26 using either capillary flow (capillary underfill), no-flow underfill, or injection molding (molding compounds) to form the package structure 10.
As shown in FIG. 1, in the case of packaging a power semiconductor switch 12, such as an IGBT or MOSFET, typically such switches require a gate resistor 14 for each gate connection. For SiC MOSFETs especially, the resistor is not integrated into the device itself, which means that an external gate resistor 14 must be added so that the switching performance of the device 12 can be controlled. For each gate resistor 14, at least one associated copper shim 24 is also added to serve as a vertical electrical connector to the multi-layer ceramic substrate. In existing packaging techniques, the addition of each of the external gate resistors 14 and the shims 24 is done individually via a pick and place operation. Accordingly, numerous, discrete pick and place operations are required to position the external gate resistors 14 and the shims 24 into adhesive 18, leading to increased fabrication time, yield issues, and increased cost associated with the use of individual shims.
Accordingly, it would be desirable to provide a new electronics packaging technology that addresses the aforementioned drawbacks associated with existing pick and place operations for providing each of the individual external gate resistors and the shims when packaging power semiconductor switches. It would further be desirable for such a packaging technology to provide a simplified manufacturing process, lower cost, and enable pre-testing of the resistors and shims prior to embedding the components within the package structure.